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Core Design Engineer
上海

Responsibilities

1. Develop micro-architecture, write micro-architecture spec and other documents
2. Write RTL code, meet the function target and have good performance/power/area efficiency
3. Apply low power, DFT, DFD and other digital design techniques
4. Work with DV team to improve test plan and debug failed tests
5. Clean Lint, timing and other issues
6. Participate in silicon debugging

Qualifications

1. Master in electrics or computer engineering
2. At least 3 years working experience in ASIC logic design
3. Expert of Verilog RTL design
4. Experience of large digital ASIC project
5. Familiar with front-end EDA tools and flows
6. Programming skill in SystemVerilog, C/C++, perl, Tcl/tk, Python, etc. is preferred
7. Familiar with Linux Environment
8. Have one or some of the following design experience: memory controller, graphics, fabric, microprocessor

申请工作
分享此职位
软件工程师 – 驱动
2020.12.31
上海/西安/南京
软件工程师 – 编译器
2020.12.31
上海/西安/南京
销售经理
2020.12.31
上海

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