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Design Verification Engineer
上海

Responsibilities

1. Understand and closely discuss with architects / designers for hardware arch and micro-arch
2. Make up Block / IP / SOC level verification plan (methodology / testbench / testplan / coverage / …) and improve cross environment reuse
3. Develop and debug testbench, tests and drive verification closure with coverage and other sign-offs
4. Develop and verify reference C-model for functional and performance purpose
5. Develop flows / tools to improve work efficiency
6. Communicate with software team for SW-HW interaction and code sharing

Qualifications

1. Computer Science, Electrical Engineering, Micro-Electronics related majors are preferred
2. 2+ years verification work experience (Bachelor/Master/PHD)
3. Good at Verilog/SystemVerilog/UVM/C/C++/Python
4. Good background in computer architecture is a plus
5. Familiarity with machine learning and deep learning is a plus
6. Familiarity with GPU computing (CUDA, OpenCL, cuDNN, TensorRT) is a plus
7. Good problem-solving ability is desired
8. Good communication skill is desired
9. Good team working skill is desired

申请工作
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